simple 8-bit zisc implementation |

More complicated target is to build around 1 ns cycle time implementation 16 x 16 multi unit (around 128 BOPS).

Because for genericity and optimization reasons registers need to be within known addresses, it would be possible to arrange registers within functionality groups, and create register address spaces.
There might be for example 3 integer mul units within some component, and other does have only one unit, so it might be possible to either (1) reconvert the code to both of the components or (2) try to map 3 register operations into 1 register on runtime.
If the registers are mapped within same address range, it would be possible to analyze the code so that converting is possible.